5-Bit PLC SSDs Not Coming Until 2025, or Later: Western Digital

Source: Tom's Hardware added 12th Jun 2021

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(Image credit: Western Digital)

Both Intel and Toshiba have become increasingly confident in their projections for the debut of PLC flash, which packs in five bits per cell to reduce SSD pricing, but Western Digitial recently downplayed the feasibility of PLC SSDs before 2025.

WD says this type of memory will only become viable sometime in the second half of this decade when SSD controllers become more advanced. The claim contradicts other 3D NAND suppliers that believe 3D PLC SSDs could rival hard drives in the next few years. 

Each new type of flash brings reduced SSD pricing, but as we’ve seen with QLC NAND, that can lead to big reductions in endurance and performance. That takes some of the shine off of a future transition to PLC (Penta Level Cell) flash that packs in five bits per cell to reduce pricing but results in even lower endurance and performance.

“I expect that transition [from QLC to PLC] will be slower,” said Siva Sivaram, Western Digital’s technology and strategy chief, at Bank of America Merrill Lynch 2021 Global Technology Conference (via SeekingAlpha). “So maybe in the second half of this decade we are going to see some segments starting to get 5 bits per cell.” 

TLC flash is the most widely used variant today, and while there are 3D QLC NAND chips available, they aren’t as widely used. Western Digital expects this to change only with its BiCS6 NAND memory and new controllers/firmware. 

“We think that QLC across the broad segment will happen in the next [BiCS 6 generation, when] the majority of bits will switch over to QLC in the marketplace,” said Sivaram. “[…]In the next two years plus we are going to see the rapid acceleration of QLC adoption.” 

Modern SSD controllers powered by Arm’s Cortex-R8 cores can handle advanced error correction (4KB LDPC) algorithms while ensuring decent performance, but 3D PLC flash will require even more complex error correction, and hence more compute horsepower from the controller. The controller will also have to support more redundant capacity and robust wear-leveling. 

“The incremental gain is not quite as much when we are going from 4 to 5 bits on the same cell, so you are getting [25%],” said Sivaram. “To get that gain you are sacrificing a lot, you need additional redundancy, additional ECC, so the net gain supposed to the performance loss may not be quite as desirable.” 

Arm introduced its 64-bit Cortex-R82 core for next-generation SSD controllers in September 2020. Arm says the design is 1.74x ~ 2.25x faster than the Cortex-R8 in real-world applications and 21% and 23% faster than the Cortex-A55 in SPECint2006 and SPECfp2006, respectively. The Cortex-R82 is designed to run in clusters with up to eight cores, so controller makers could build rather formidable processors based on the new core, which will be quite handy for PLC SSDs.  

There is a catch, though. The first controllers with the Cortex-R82 (probably due sometime in 2023 or 2024) will likely be aimed primarily at high-end drives with in-storage compute capabilities, and not on high-density SSDs featuring cheap 3D PLC flash. As a result, 3D PLC flash is unlikely to become mainstream any time soon. 

There are certainly plenty of challenges involved with moving to PLC flash. For example, 3D PLC NAND can store five bits per cell (5 bpc), a 25% increase over quad-level cell (QLC) flash, and a 66% increase over the triple-level cell (TLC) flash memory used today.

To do so, NAND cells have to store 32 distinct voltage levels, and SSD controllers have to read them properly and record them fast. In contrast, TLC uses eight voltage levels, and QLC uses 16 voltage levels. In addition to the complexity of PLC 3D NAND cells, challenges like cell-to-cell interference and temperatures make it harder to read data. 

To offer decent performance and endurance characteristics, 3D TLC-based SSDs use 120 bit/1KB or even 340 bit/2KB LDPC ECC algorithms that are already quite complex. In addition, manufacturers also implement static and dynamic wear-leveling, RAID ECC, and overprovisioning to further maximize endurance.  

With 3D QLC-powered SSDs, we’ll need support for 2KB and 4KB LDPC codewords, more complex wear-leveling, and more overprovisioned capacities. Furthermore, memory makers also have to change the design of their cells (e.g., use slightly different materials, etc.) to reliably store 16 voltage levels.

All of this means that we’ll see PLC SSDs later rather than sooner, largely due to needed advances that aren’t directly associated with manufacturing the flash itself. 

Read the full article at Tom's Hardware

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media: Tom's Hardware  
keywords: Memory  NAND  SSD  TLC  

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