Patch notes for a new update of HWInfo64 have confirmed that Intel’s next generation of CPUs, codenamed ‘Alder Lake’ will use gear modes on its memory controller, similar to Intel’s current Rocket Lake processors. The patch notes indicate that HWInfo64 can now report which gear mode an Alder Lake CPU is actively using.

Gear modes were introduced with the Rocket Lake architecture, and they allow users to change the way the memory controller behaves in order to achieve higher compatibility with more memory kits and higher RAM speeds.

You are given the choice of two gear modes with Rocket Lake. Gear 1 will allow the memory controller to operate at the same frequency as the system’s memory (known as a 1:1 ratio), allowing for the lowest latency possible. Gear 2, on the other hand, will cut the memory controller’s speed in half (2:1 ratio), compared to the system’s memory frequency allowing the memory controller to operate significantly higher frequency RAM.

However, because Gear 2 cuts the memory controller’s clock speed in half, your memory latency gets penalized, so this mode is only beneficial for workloads that are very sensitive to memory bandwidth over memory latency, which is found mostly in professional applications. If you’re a gamer or casual PC user, the lower latency with Gear 1 is the better choice.

What we don’t know yet is how gears will be implemented on Alder Lake. Intel could be upgrading the memory controller on Alder Lake, which would change the capabilities of each gear ratio. Or Intel might be using the same controller found on current Rocket Lake CPUs, we really don’t know at this time.

Either way, gears will most likely play a much bigger role in memory performance with DDR5 arriving on the scene. Alder Lake will be Intel’s first architecture to support not just DDR4 but DDR5 as well. With DDR5 frequencies hitting 8400MHz already, we could see a change in the way things currently stand, so that having a higher frequency at the expense of a slower memory controller speed is more important than lower latency in more situations.