Block diagram for AMD's Ryzen 5000 “Cezanne” revealed
Source: Hardware Luxx added 07th Jan 2021The appearance of a schematic block diagram of a Ryzen – 5000 processor based on the Cezanne design apparently allows some further conclusions to be drawn about the processors. Videocardz has compared the block diagram to the current Renoir design.
The Cezanne processors should use up to eight Zen 3 cores and eight compute units based on the Vega architecture. With regard to the cores and CUs, the full configuration is identical to the Renoir processors, which, however, use Zen 2 cores. Major changes can be seen in the block diagram, not all of which can be explained with the Zen 3 design and larger caches.
L2 / L3 cache | Die-Size (SoC / CCD) | transistor density | |
Renoir | 4 MB / 8 MB | 156 mm² | 62, 82 MTr / mm² |
Matisse | 4 MB / 32 MB | 74 mm² | 52, 70 MTr / mm² |
Cezanne | 4 MB / 16 MB | ? | ? |
Vermeer | 4 MB / 32 MB | 80 , 7 mm² | 51 , 43 MTr / mm² |
The biggest difference between the desktop design (Matisse) and the mobile design (Renoir) The basis of the Zen 2 architecture was found in the halved L3 cache. Ultimately, a Renoir processor has 9.8 billion transistors. The size of the chip is 147 mm². All of the above processors will be manufactured at TSMC in 7 nm. AMD uses a process called “Deep Ultraviolet (DUV) Photolithography” – you can still get by without EUV exposure (Extreme Ultraviolet).
For Cezanne the L3 cache compared to Renoir is set to 16 MB doubled, but will still be half the size of the current desktop design (Vermeer). In the comparison between Matisse and Vermeer you can see that the CCD of 74 on 80, 7 mm² has grown, what with the changes in Zen -3 design related. Alone the 32 Occupy MB of L3 cache 27 mm² in space. Accordingly, it should be for 16 MB about 13, 5 mm².
Currently we do not yet know any data such as the number of transistors and the size of the Cezanne processors. According to initial estimates based on the block diagram, Cezanne should be around 175 mm² come, which is certainly partly due to the larger L3 cache.
The Zen 3 architecture and the associated changes in the cache hierarchy apparently have an impact on the overall design and size of the chip. However, there are likely to be other factors. AMD limited the Renoir processors to PCI-Express 3.0 and the mobile variants are also only eight instead of the otherwise freely available 20 Lanes available. This is justified with the lower power consumption, which is of course of particular importance in the mobile segment.
It is not known whether the Cezanne processors will support PCI-Express 4.0. It should be another 16 + 4 + 4 configuration for the lanes indicate whether AMD will reproduce them for the mobile variants limited to eight for connecting a dedicated GPU is also unknown. The desktop variants from Cezanne will certainly again offer more PCI Express lanes than the mobile variant.
On 11. January, AMD will give a keynote to the CES 2017 organize. The presentation of the Cezanne processors and the corresponding notebooks is expected there. These are then to be combined with the mobile Ampere GPUs from NVIDIA. When the corresponding notebooks will be available is still in the stars. However, there are indications that we will see a tense delivery situation with the mobile Ryzen processors, which, together with the also scarce ampere GPUs, will affect the entire notebook market. Partly the notebooks are therefore still with Ryzen – 4000 – and Core – 10000 – processors – so of the previous generation – to be equipped.