The Chinese company Espressif sells the widespread WLAN microcontrollers ESP 8266 and ESP 32 for IoT and smart home devices. In the upcoming ESP 32 – C3 calculates instead of one 32 – Bit core from Tensilica (Xtensa LX6) now one with the disclosed instruction set architecture (ISA) RISC-V.

Espressif has not yet publicly announced the ESP 32 – C3, but the draft can be found on the company’s website of a data sheet in version 0.3. Accordingly, the ESP 32 – C3 in terms of functionality is between the simplest ESP 8266 and the more complex ESP 32 – versions.

In the ESP 32 – S2 Espressif already builds a RISC-V core, but only as a particularly efficient “Ultra Low Power (ULP) co-processor; a programming manual has been published for this purpose.

RV 32 IMC with 160 MHz When the ESP 32 – C3 or radio modules equipped with it should come onto the market is unclear. Espressif may be holding the news until the RISC-V Summit, which starts on December 8th.

According to esp pre-sheet 32. com puts Espressif in the ESP 32 – C3 to a RISC-V core the specification RV 32 IMC with up to 160 MHz clock. 400 KByte SRAM are installed at the factory. A Serial Peripheral Interface (SPI) is used to connect the flash memory, the chip version ESP – C3FH4 has 4 MByte Flash on board.

The WLAN part apparently remains unchanged and continues to only transmit in the 2.4 GHz band (1 × 1, 150 Mbit / s). The Bluetooth part should now be compatible with basic functions of Bluetooth 5.0 and with Bluetooth Low Energy (Bluetooth LE, BLE).

In addition, a USB 1.1 device interface is built in, which can also be used as a JTAG interface can serve. 22 Pins can be used as GPIO and for common interfaces such as I²C, I2S and TWAI (CAN bus according to ISO 11898 – 1).

The ESP 32 – C3 contains security functions to better protect the code of networked IoT devices against manipulation. An AES-XTS unit can encrypt the flash memory and there is a secure boot function and hardware units for AES – 256 , SHA – 256 and RSA (up to 3072 bit) .

(ciw)