The days of open-source GPUs may soon be upon us. The RISC-V architecture enables small companies to develop purpose-built processors and microcontrollers without paying a royalty. There are numerous free and commercial IP building blocks for RISC-V-based system-on-chips (SoCs), but the portfolio lacks a graphics option. This will change in a few years as a group of enthusiasts has started developing an open-source GPU based on the RISC-V architecture.
At this point, there are no plans to compete against AMD, Arm, Imagination, and Nvidia in the foreseeable future. Instead, the group plans to develop a scalable fused CPU-GPU ISA that could scale from simplistic microcontrollers all the way to advanced GPUs supporting ray tracing, machine learning, and computer vision applications with custom hardware extensions.
On a high level, RV64X-designed GPUs use a basic RV32I or RV64I core that supports new instructions built on the base vector instruction set. Initially, it will use an RV32I core, but eventually, an RV64I core will replace it as the goal is to create an area-efficient design with custom programmability and extensibility that could be used for CPUs, GPUs, and VPUs, writes Jon Peddie for EE Times.
To properly process graphics, the basic RISC-V core will support new graphics and machine learning specific — RV32X — data types, including scalars (8, 16, 24, and 32 bit fixed and floats, vectors (RV32-V), and matrices (2×2, 3×3, and 4×4); vector/math instructions; pixel/texture instructions; frame buffer instructions; a special register set (featuring configurable 136-bit vector registers); and some graphics-specific instructions. Initially, the graphics core will support the Vulkan API, but the group strives to make it DirectX (shader model 5) and OpenGL/ES-compliant.
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The RV64X group says that its graphics processor will implement a standard graphics pipeline in microcode, but it will also be able to add custom rasterizers (splines, SubDiv surfaces, patches) and custom pipeline stages to support features not supported by commercially-available GPU designs.
The group proposes an RV32X reference implementation that features a hardware texture unit (i.e., the Larrabee lesson has been learned), a special function unit, a 32KB L1 cache, an 8K uCode SRAM cache, and four 32-bit DSPs/ALUs that can process FP32 and INT32 data, reports HardwareLuxx. The reference design will most likely be implemented using an FPGA.
The RV64X project is at its early stages of development and it will take at least a couple of years before the specification will be finalized and any hardware implementation emerges, believes Jon Peddie, the president of Jon Peddie Research. In fact, even the specification is subject to change based on stakeholder and community input, so it is way too early to discuss performance or any other matters.
The group, which calls itself RV64X as its plan is to develop a 64-bit universal ISA, is led by Atif Zafar from Pixilica, Grant Jennings from GOWIN Semiconductor, and Ted Marena from CHIPS Alliance and Western Digital.
Initially, an RV64X-designed graphics controller will be used for very simple microcontrollers that require extremely small units due to cost concerns. But as the design evolves, its descendants could address more demanding applications years and generations from the initial implementation.