The Intel Alder Lake-S leaks keep rolling in. This time, another Geekbench database entry has been spotted, detailing an unannounced, upcoming Intel Alder-Lake S 16C/24T CPU. 

Based on the 10nm process node, Intel Alder Lake-S will be the company’s first architecture featuring support for DDR5 memory and PCIe 5.0. This processor architecture will feature a hybrid core design, featuring small Tremont cores and big Sunny Cove cores that seem to have hyper-threading as per the Geekbench 5 entry found by @TUM_APISAK.

Intel Corporation AlderLake-S ADP-S DRR4 CRB

Intel 0000

Processor, 16 Cores, 24 Threads

GenuineIntel Family 6 Model 151 Stepping 0https://t.co/5MX0H3U9UP pic.twitter.com/Z0ewFGqeEV

— APISAK (@TUM_APISAK) December 29, 2020

The processor listed in the Geekbench 5 has 16 cores (8x big and 8x small) and 24 threads, with a reported base clock of 1.38GHz, and a maximum clock of 17.6GHz. The 17.6GHz maximum clock is probably an error and should be the turbo frequency of one set of cores after being divided by 8. Apparently, Geekbench 5 software doesn’t handle hybrid architectures such as Alder Lake very well.  This entry also details the cache structure of this processor, which comes with 960KB of L1 cache, 1.25MB of L2 cache per core, and 30MB of L3 cache, similar to what we’ve found in the SiSoftware entry.

Regarding the scores, given how low the reported clocks are, we should not take them seriously. Nonetheless, it scored 996 in single-core workloads and 6931 in multi-core workloads. Compared to the Intel Rocket Lake-S Core i7-11700K Geekbench 5 scores that we have reported recently, that’s almost half of the single-core score and over a third less in the multi-core score. Future engineering samples and retail versions of these processors should score considerably higher than this.

Intel Alder Lake-S CPUs are expected to release in late 2021.

KitGuru says: We’re still in early days for Alder Lake-S, so we can expect very different scores later in 2021 as improved engineering samples begin to surface. 

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