The consortium PCI SIG announced that it has reached an important milestone in the definition of the PCI Express 6.0 : the version 0.7 of the specification in fact marks the completion of the draft , therefore the technology has been defined and electrical specifications have been validated with test chips – changes are therefore no longer permitted. It can be said that PCIe 6.0 is ready and will be finalized in the course of 2021 , when completing two further steps, version 0.9 and version 1.0.

Version 0.9 is referred to as the final draft, and is where members of the PCI-SIG carry out internal reviews of the technology in order to adapt it to their respective intellectual properties and patents. Version 1.0 marks the final release of the technology. PCI Express 6.0 will increase the transfer rate from data to 64 GT / s per pin, twice as many as 32 GT / s of PCIe 5.0.

To increase the transfer rate and bandwidth, the new interface adopts PAM4 , i.e. the modulation of the pulse width at four levels , a solution also chosen by Micron for the GDDR6X memories of the GeForce RTX cards 3000. PCI Express 6.0 also offers a low latency technology called forward error correction (FEC) to ensure greater efficiency in the use of bandwidth. As always, version 6.0 will also guarantee backwards compatibility with previous generations .

Although the work can be said to be completed, the PCI Express 6.0 will not debut concretely until before 2023 – 2024 : the main hardware manufacturers, from AMD to Intel, should in fact adopt the PCI Express 5.0 only between the late 2021 and the ‘beginning of 2022, obviously starting from the server sector, and then thinking about PCIe 6.0 only later.