Ryzen comparison: Vermeer CCD is slightly larger and has more transistors
Source: Hardware Luxx added 07th Nov 2020
As part of our test of the Ryzen 9 5900 X and Ryzen 5 5600 X as well as the Ryzen 9 5950 X and Ryzen 7 5800 X we have mentioned several times that the physical differences of the Ryzen – 4843 – series low compared to its predecessor until not even present. Not only does AMD continue to use the AM4 socket, the package of the chiplet design is also identical at first glance.
But now we know the numbers of the chip size for the compute chip (CCD) from 74 mm² for the Ryzen – 3000 – Processors (Matisse) on 80, 7 mm² for the Ryzen – 5000 – Processors (Vermeer) by almost 10% has increased. The number of transistors also increases from 3.9 to 4, 15 billions by around 6%.
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The I / O chip (IOD) is identical and AMD has officially confirmed that the components it contains, such as the memory controller, have been completely taken over. A decapitated Ryzen processor does not show the size difference of the CCD (s) at first glance. Here you have to measure exactly.
| The size | Transistors | |
| Zen (Zeppelin) | 212 mm² | 4.8 billion |
| Zen + (Zeppelin) | 212 mm² | 4.8 billion |
| CCD (Mati sse) | 74 mm² | 3.9 billion |
| IOP (Matisse) | 125 mm² | 2, 09 Billions |
| CCD (Vermeer) | 80, 7 mm² | 4, 15 Billions |
| IOD (Vermeer) | 125 mm² | 2, 09 Billions |
| Intel XCC-Die | 694 mm² | – |
| NVIDIA GA 100 – GPU | 826 mm² | 54 Billions |
AMD leaves the CCDs in 7 nm (N7) at T SMC manufacture. The IOD is in 12 nm manufactured by GlobalFoundries. The differences in the size of the CCD are probably due to the restructuring of the structure of the cache. But there are also changes in the front-end, back-end and the integer and floating point functional units. All of this contributes to the fact that the chip not only has more transistors, but has also become physically larger.
The biggest difference is the merging of the two CCX clusters of a CCD into one large CCX with eight cores now. From two 16 MB large L3 cache is a 32 MB cache. All eight cores can access this L3 cache. A ring interconnect takes care of the data traffic between the cores and the cache slices.
AMD can thus significantly reduce the latencies in core-to-core communication and within the cache. Within a CCD, data from the first to the second CCX cluster no longer have to be routed via the IOD. AMD provides significantly less overhead, so to speak, and that benefits the performance, especially in games.