keyword: 5G

leaked-specs-of-the-samsung-galaxy-s21-suggest-the-ultra-model-will-support-s-pen

Leaked specs of the Samsung Galaxy S21 suggest the Ultra model will support S Pen

Samsung’s Galaxy S21 is anticipated to debut in January, and Android Police has a slew of leaked specs for the forthcoming phone. The usual caveats about leaked information apply, but most of it lines up with what you’d expect.

Android Police says its leaker confirmed that earlier renders of the S21— which show the same camera bump of the Galaxy S20— are accurate.

Render of the supposed Galaxy S21
Steve Hemmerstoffer

There are three S21 models expected— a standard, a Plus and an Ultra. According to Android Police, the S21 will have a 6.2-inch display, the Plus will be 6.7 inches and the Ultra will reportedly have a 6.8-inch display. Android Police says the leaked info confirms that the S21 Ultra will support the S Pen, but the S Pen won’t be included with the phone.

According to the leaked info, all three phones will have either a Snapdragon 875 or Exynos 2100 processor, and all will have One UI 3.1, based on Android 11.

The camera is anticipated to vary by phone; both the S21 and S21 Plus are expected to have a 12MP main lens, a 12MP ultra wide lens and a 64MP telephoto lens; the Ultra will have a 108MP main lens, a 10MP 3X optical telephoto lens and 10MP 10x optical telephoto lens, and a 12MP ultra wide lens.

The phones are all expected to have 5G, with the S21 and Plus both with Wi-Fi 6 and Bluetooth 5.1, and Wi-Fi 6E in the Ultra.

The batteries also will vary depending what model of the Galaxy S21 you choose: the S21 battery will have 4,000 mAh, the Plus will have 4,800 mAh, and the Ultra will have 5,000 mAh, according to the leak.

The colors available for the S21 are expected to include Phantom Violet, Phantom Pink, Phantom Gray, and Phantom White; the Plus will come in Phantom Silver, Phantom Black, and Phantom Violet; and the Ultra will only be available in Phantom Silver and Phantom Black, Android Police says.

No word yet on pricing for any of the S21 models.

ifixit’s-iphone-12-mini-teardown-looks-at-how-apple-fit-so-much-into-such-a-tiny-device

iFixit’s iPhone 12 mini teardown looks at how Apple fit so much into such a tiny device

Orders for the new iPhone 12 mini have started arriving for customers, and the team at iFixit did a two-part teardown—of both an EU and US model— to figure out how Apple managed to include 5G hardware and the usual iPhone components into such a little device.

The first thing you notice looking at the internal images is the smaller battery in the mini, which measures up to similar iPhone models surprisingly well, iFixit finds, with 8.57 Wh.

“That’s more juice than the iPhone SE 2020‘s 6.96 Wh, but understandably short of the 10.78 Wh of the standard 12 it’s stacked on top of,” iFixit notes. It’s less than the 10.78 Wh of the iPhone 12 battery, though.

The iPhone 12 mini is on the left, the iPhone 12 on the right
iFixit

The Taptic Engine, speakers, and MagSafe ring are all included in the mini in smaller versions to save space. But Apple managed to fit the same-sized camera as its other iPhone models into the mini, which iFixit suggests may have come at the expense of battery life— something The Verge’s Dieter Bohn encountered in our iPhone mini review.

The mini camera has the same ƒ/1.6 wide-angle and ƒ/2.4 ultra wide-angle cameras found in the iPhone 12, the teardown shows.

iPhone 12 mini
iFixit

Overall, iFixit found the iPhone 12 mini to be quite similar to its larger counterparts: “The iPhone 12 mini is a small phone with big ambitions. We’re surprised by how familiar the internals look compared to other iPhones this year, given the differences in size among them.”

Check out iFixit’s full iPhone 12 mini teardown here. And see what The Verge reviewers think of the new iPhone models:

new-x-nand-tech-detailed:-slc-speed-at-qlc-capacity-and-pricing

New X-NAND Tech Detailed: SLC Speed at QLC Capacity and Pricing



(Image credit: Shutterstock)

During the three-day virtual Flash Memory Summit for 2020, CEO and founder of NEO Semiconductor, Andy Hsu, gave a detailed presentation covering the company’s new X-NAND flash architecture that promises to combine the speed of SLC flash with the density and low pricing of QLC flash.

NEO Semiconductor was founded in 2012 in San Jose, CA, and has twenty memory-related patents to its name. The company first revealed its X-NAND in 2018 as a storage solution for the emerging markets of AI and 5G but has now shared the deep-dive details. 

(Image credit: Tom’s Hardware)

X-NAND promises intriguing performance numbers: The company claims it can do random read and write workloads 3x times faster than QLC flash, and beat it by 27x/14x for sequential read and write workloads, respectively (see above). This is achieved with a far smaller die that’s roughly 37% the size of a 16-plane design (see below). There is some flexibility here as speed and die size reduction can be balanced as needed. Still, X-NAND offers particularly high levels of parallelism even for smaller form factors, as you would find in a smartphone or an M.2 drive. The company also claims this can be achieved without impacting endurance or cost, all while consuming very little power.

(Image credit: Tom’s Hardware)

As the NAND market moves to cheaper but slower flash to increase density, for example, from 3-bit TLC to 4-bit QLC, performance and endurance are inherently reduced. Read and write latencies increase, which can reduce sequential write performance. That’s especially detrimental for datacenter and NAS applications. 

Consumer QLC drives tend to rely heavily on SLC caching, which consists of part of the native flash operating in single-bit mode. Still, enterprise workloads do not allow for sufficient idle time to migrate written data from the SLC buffer to primary QLC storage. 

Instead, X-NAND offers a way for the flash to maintain SLC performance throughout by allowing for simultaneous SLC and QLC write modes (see below).

(Image credit: Tom’s Hardware)

Hsu was quick to point out that higher-density flash is growing at a rapid rate, citing Western Digital’s anticipation that up to 50% of the market would be comprised of QLC by 2024. His goal with X-NAND was to make sure it used a conventional NAND process with no structural changes, no additional manufacturing costs, and fast development with quick sampling as a solution based on current NAND. That strategy is designed to speed up the adoption of QLC, especially for the data center as flash performance would no longer fall drastically behind I/O speeds. Further, X-NAND programming and erase policies are designed to drastically improve endurance over QLC flash (see below). 

(Image credit: Tom’s Hardware)

X-NAND achieves these gains by going from a 16KB page buffer per plane to a 1KB page buffer per plane, but with sixteen times the planes, as one example. 

A plane tends to be the smallest unit of interleaving for flash, with one or more planes per flash die. The page buffer holds data in transit, like read or write data, between the bus and the flash. A flash die is divided into planes containing bit lines or strings of cells (see above), so planar division can reduce the bit line’s length, which helps boost performance. This technique is further enhanced by shielding between adjacent bit lines to reduce settling time when reading or verifying a program (see below). Write performance is increased because up to sixteen bit lines can be programmed in parallel. 

(Image credit: Tom’s Hardware)

X-NAND has six primary features: multiple bit line writes, multi-plane QLC programming, program suspend, multi-BL reads, single latch QLC reads, and the aforementioned SLC/QLC parallel programming. Depending on the implementation, this can improve program throughput substantially as multiple planes can be used in the programming sequence (see below). 

The use of multiple banks allows for simultaneous SLC and QLC programming, ensuring the SLC pages are never full, while data can be programmed to the QLC pages at SLC speed. The program suspect function enables using the internally shared inter-page buffer data lines or I/O bus to minimize additional latency. Reads are improved by having a plane latch the read per bit line, with DRAM-like refreshing of data in a non-destructive way due to high capacitance. 

(Image credit: Tom’s Hardware)

X-NAND can work with any number of existing NAND layouts, which increases its flexibility and ease of conversion (see below). NEO Semiconductor intends for the tech to be cost-effective, fast, and easy to implement with existing designs. 

The company says it is especially useful with higher-density flash like QLC because it can leverage the high capacity with a balance of high performance and lower die area while being affordable with good endurance and power consumption. The tech is aimed at embedded devices, AI, and the cloud, including NAS, data center, and edge computing. 

(Image credit: Tom’s Hardware)