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Pine64 Release Quartz64, Announces SOQuartz Module

(Image credit: Pine64)

Pine64 today announced that its Quartz64 single-board computer is now available and revealed a system-on-module (SoM) based on that design called the SOQuartz.

The company said in February that the Quartz64 model-A would feature a Rockchip RK3566 SoC, a veritable smorgasbord of ports, and between 2GB and 8GB of LPDDR4 memory in a board measuring 5.2 x 3.1 x 0.7 inches (133 x 80 x 19mm).

Pine64 isn’t offering any Quartz64 models with 2GB of RAM at launch, however, opting instead for a 4GB model that costs $60 and an 8GB model that costs $80. It didn’t say when a base model featuring 2GB of memory is expected to debut, either.

The Quartz64 model-B is supposed to arrive “in the coming months.” Pine64 said the model-B will feature either a “BL-602 RISC-V 802.11n and BLE 5.0 module, currently undergoing open-sourcing, or an AP6256 802.11ac WiFi + Bluetooth 5.0 module.”

Meet the SOQuartz

Quartz64 laid the foundation for a new SoM called the SOQuartz. The new device should look awful familiar to Raspberry Pi Compute Module 4 owners.

”On the bottom of the PCB you will find the now industry-standard 100-pin high density connectors,” it said. ”This means that it will be possible to use the SOQuartz as a drop-in replacement for the most popular solution on the market.”

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Put directly: SOQuartz could possibly be a drop-in replacement for the Raspberry Pi Compute Module 4 as the pair appear to be based on the same connector, but hardware and software compatibility is still unknown at this time.

Pine64 said the SOQuartz will feature the RK3566 SoC, the Azurewave AW-CM256SM WiFi 802.11ac Bluetooth and WiFi module with a U.FL antenna connector, and the option of using its eMMC modules or shipping with soldered-on storage.

SOQuartz appears to be in the prototyping stage. Pine64 didn’t offer additional details about the SoM’s specs, expected release date, or price.

RISC-V Evolving to Address Supercomputers and AI

(Image credit: ORNL)

The open source RISC-V instruction set architecture is gaining more mainstream attention in the wake of Intel’s rumored $2 billion bid for SiFive, the industry’s leading RISC-V design house. Unfortunately, RISC-V has long been relegated to smaller chips and microcontrollers, limiting its appeal. However, that should change soon as RISC-V International, the organization that oversees the development of the RISC-V instruction set architecture (ISA), has announced plans to extend the architecture to high performance computing, AI, and supercomputing applications.

The RISC-V open-source ISA was first introduced in 2016, but the first cores were only suitable for microcontrollers and some basic system-on-chip designs. However, after several years of development, numerous chip developers (e.g., Alibaba) have created designs aimed at cloud data centers, AI workloads (like the Jim Keller-led Tenstorrent), and advanced storage applications (e.g., Seagate, Western Digital).

The means there’s plenty of interest from developers for high-performance RISC-V chips. But to foster adoption of the RISC-V ISA by edge, HPC, and supercomputing applications, the industry needs a more robust hardware and software ecosystem (along with compatibility with legacy applications and benchmarks). That’s where the RISC-V SIG for HPC comes into play.

At this point, the RISC-V SIG-HPC has 141 members on its mailing list and 10 active members in research, academia, and the chip industry. The key task for the growing SIG is to propose various new HPC-specific instructions and extensions and work with other technical groups to ensure that HPC requirements are considered for the evolving ISA. As a part of this task, the SIG needs to define AI/HPC/edge requirements and plot a feature and capability path to a point when RISC-V is competitive against Arm, x86, and other architectures.

There are short-term goals for the RISC-V SIG-HPC, too. In 2021, the group will focus on the HPC software ecosystem. First up, the group plans to find open source software (benchmarks, libraries, and actual programs) that can work with the RISC-V ISA right out of the box. This process is set to be automatized. The first investigations will be aimed at applications like GROMACS, Quantum ESPRESSO and CP2K; libraries like FFT, BLAS, and GCC and LLVM; and benchmarks like HPL and HPCG.

The RISC-V SIG-HPC will develop a more detailed roadmap after the ecosystem is solidified. The long-term goal of the RISC-V SIG is to build an open-source ecosystem of hardware and software that can address emerging performance-demanding applications while also accomodating legacy needs.

How many years will that take? Only time will tell, but industry buy-in from big players, like Intel, would certainly help speed that timeline.

Intel Offers $2 Billion for RISC-V Chip Startup SiFive: Bloomberg

(Image credit: Intel)

According to Bloomberg’s sources, Intel has offered $2 billion for startup chip designer SiFive, though neither company has officially acknowledged the offer. SiFive is the leading designer of chips based on the open source RISC-V architecture that has coincidentally attracted much more interest in the wake of Nvidia’s ongoing acquisition of Arm for $40 billion. The reports of the possible SiFive acquisition come on the heels of SiFive’s announcement that it will collaborate with Intel’s newly-christened foundry services.

SiFive, most recently valued at $500 million, is reportedly considering takeover offers from multiple firms and it may still choose to remain an independent outfit. Much of the new interest in SiFive and RISC-V stems from firms looking to avoid any potential pitfalls due to Nvidia’s potential control of Arm.

RISC-V is an open source instruction set architecture (ISA) for RISC chips that discards the traditional notion of licensing fees associated with designing chips around a certain ISA, as we see with Arm. The ISA is maintained by the non-profit RISC-V International organization comprised of more than 1,000 members in 50 countries.

RISC-V is most commonly used in microcontrollers and small, simple chips, which has earned it quite the industry uptake with companies like WD, which ships over two billion RISC-V controllers a year in its products. The RISC-V organization plans to evolve the standard to accommodate faster chips for high-performance applications in the future.

Chinese chip firms have shown a keen interest in RISC-V chip designs in the wake of US restrictions on their use of Arm designs due to US national security interests. Naturally, RISC-V’s open source licensing, which eschews fees, and the fact that the company is incorporated in Switzerland and doesn’t “take a political position on behalf of any geography” is enticing to Chinese firms.

Intel CEO Pat Gelsinger’s recent announcement that the company would begin licensing its own x86 processor designs to other firms as part of its new IDM 2.0 initiative was surprising, and the company even revealed that it would be open to fabbing third-party Arm designs in its new custom foundry outfit, Intel Foundry Services (IFS).

If the reports are true, it’s natural to expect that Intel will look to add RISC-V designs to its own arsenal and also offer custom designs to customers of its new foundry services business, all of which ties in nicely with the company’s pledge to help “re-shore” semiconductor manufacturing in the US.

Huawei’s HiSilicon Develops First RISC-V Design to Overcome Arm Restrictions

(Image credit: Panasonic)

In a bid to overcome US restrictions on its Arm designs, Huawei’s HiSilicon has turned to the open-source RISC-V architecture and has even released its first RISC-V board for Harmony OS developers. Due to being blacklisted by the U.S. government, Huawei and its chip division HiSilicon do not have access to development and production technologies designed in America. The restrictions include many Arm processor architectures, including those used in various microcontrollers that Huawei uses widely.

HiSilicon’s HiSilicon Hi3861 development board is based on the company’s own Hi3861 controller. Huawei’s documentation doesn’t disclose exactly what the chip does, but it describes it as a main controller chip. The Hi3861 chip is accompanied by a serial port controller as well as a USB-C port. Among the more important aspects, the Hi3861 seems to have all the logic that enables USB-C functionality (e.g., synchronization and port alignment) and GPIO (general-purpose) pins.

(Image credit: HiSilicon)

Overall, the HiSilicon Hi3861 development board has rather vast (at least Raspberry Pi-like) capabilities, but not for a world that Huawei’s HiSilicon is used to, at least in terms of public opinion.

(Image credit: HiSilicon)

The Hi3861 is aimed mostly at the IoT market, whereas HiSilicon’s development efforts were historically aimed at high-margin smartphones, tablets, PCs, and embedded systems. But Huawei needs computing platforms to use for its other devices, so the HiSilicon Hi3861 is just what the doctor ordered at this time.

When it comes to high-volume products made by Huawei, a non-Arm-based chip makes exceptional sense and also gives the company experience working with an open-source architecture. Only time will tell if the company uses its RISC-V experience to develop other, more powerful devices.

Low Cost Raspberry Pi Alternative RISC-V Board Starts Crowdfunding

(Image credit: Wu Caesar)

The 64bit RISC-V Raspberry Pi alternative we wrote about last month has turned up again, this time on Indiegogo, with a new name. The Nezha board, named after a protective deity in Chinese mythology, was also briefly listed for purchase directly from AliExpress but it seems that it has since been taken down. Nezha offers a low cost, point of entry into the RISC-V world for developers eager to try a new IoT platform.

(Image credit: Wu Caesar)

Buyers get a single-core Allwinner D1 64-bit RISC-V processor running at 1GHz, backed by 1GB of DDR3 RAM and 256MB of flash storage. The 40 pin GPIO looks to be Raspberry Pi compatible, but we would bet against being able to use HATs and other add-ons with it. Allwinner’s favoured OS is Tina, a fork of OpenWrt, itself a Linux project targeting embedded devices such as routers. It’s been around since 2004 and is optimized to fit in tiny spaces, generally being configured through the CLI. Debian 11 with a lightweight desktop environment is also available, while Fedora, Gentoo, and Ubuntu are also being worked on.

The board is available in a few bundles, such as the one with a 720p USB camera board, or an eight-inch capacitive touchscreen. A ‘full suite’ bundles those two with a six-mic array, that also comes with five hardware buttons, for around $170.

Performance isn’t expected to be great, as the board doesn’t feature a 3D GPU and the 1GHz single-core CPU will be weak in comparison to others. It’s perfect for anyone looking to play around with RISC-V architecture.

Remember that backing a crowdfunded project is not a guarantee of receiving the final product. Crowdfunding is not the same as a retail purchase and so due diligence is required before you invest.

Preliminary Apple M1 Support Added To Latest Linux Kernel

(Image credit: Apple)

Linux Torvalds has announced availability of Linux kernel 5.13 release candidate that adds preliminary support for Apple’s M1 system-on-chip along with a number of improvements to the operating system itself, reports 9to5Linux.com.

The most interesting addition to Linux kernel 5.13 is preliminary support for Apple’s M1 SoC, something that developers have been working on for months now. While Linux does support Arm and can run on various SoCs such as the Raspberry Pi, Apple’s M1 is considerably different from other processors, so making Linux run on this chip was a tough challenge.

At this point Linux 5.13-RC1 can boot on an M1-based system, but does not support all features of the SoC. For example, GPU support is still not even half-baked.

“This is just basic bring-up, but it lays a solid foundation and is probably the most challenging up-streaming step we’ll have to do, at lease until the GPU stuff is done,” said Hector Martin, a software developer, reports The Register.

Availability of Linux kernel 5.13-RC1 means that the Linux development community finds that the new build is almost ready for release, with an anticipated final release due in June / July.

“This was – as expected – a fairly big merge window, but things seem to have proceeded fairly smoothly,” wrote Torvalds in a description of the new Linux kernel version. “There’s a lot in there. […] It’s all over the place, although GPU and networking stands out. […] Outside of drivers, it’s a bit of everything: arch updates (Arm, x86 and PowerPC dominate), documentation, tooling, and obviously all the expected core kernel stuff: file systems, process handling, VM, and core networking.”

In addition to Apple’s M1, the new Linux kernel 5.13-RC1 features improved support for Arm’s Zen 3 microarchitecture, the latest Arm-based SoCs for servers, and the RISC-V architecture.

Loongson Technology Develops Its Own CPU Instruction Set Architecture

(Image credit: HKEPC)

Chinese processor developer Loongson Technology this week announced that it had developed its own CPU instruction set architecture (ISA), Loongson Architecture (LoongArch) that has nothing to do with architectures designed outside of China. Surprisingly, the first processors based on the new architecture have already been taped out and will be released commercially this year.

For many years Loongson’s processors relied on different versions of the company’s LoongISA architecture, which were subsets of the MIPS64 architecture. This approach allowed the company to maintain compatibility with software developed for MIPS64 (which includes software for supercomputers) and also introduce its own extensions to boost performance in modern applications.

By contrast, LoongArch is said to feature almost 2,000 of proprietary instructions. Meanwhile, the company said that it had removed outdated instructions not suitable for modern hardware designs to ensure low power consumption and simpler designs. In addition to the base instruction set, LoongArch features binary conversion extension instructions (LBT), vector processing extension instructions (LSX), advanced vector processing extension instructions (LASX), and virtualization extension instructions (LVZ), reports PC Watch.

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Apparently, the first CPUs to use the LoongArch are Loongson’s quad-core 3A5000 for client PCs and 16-core 3C5000 for multiprocessor servers. Previously Loongson called these processors ‘MIPS64-compatible’, so they can execute programs originally developed for previous-generation Loongson processors that relied on a superset of the MIPS64 architecture. The Loongson 3A5000 is set to ship in the first half of 2021, whereas the 3C5000 is projected to be available towards the end of the year, according to a previous report.

Loongson Technology has released its LoongArch infrastructure instruction system manual to some interested parties for evaluation, but is yet to publish it for a broader audience of software developers. Also, the LoongArch is currently evaluated by the Chinese IP agency.

(Image credit: Loongson)

China has been striving for semiconductor self-sufficiency for years now and even created its Made in China 2025 program that set the time-frame by which this self-sufficiency is set to be achieved. Analysts are skeptical that China will be self-sufficient by 2025 as far as semiconductors are concerned, but the country is moving towards its goal.

A proprietary CPU ISA is certainly a step towards self-sufficiency as Loongson no longer has to rely on Arm, MIPS, x86, RISC-V or other Western processor architectures. However, only time will tell whether the company can actually develop a competitive ecosystem for its LoongArch.

It is noteworthy that Loongson Technology has once announced plans to transit to open-source RISC-V, so if LoongArch fails, the company will have a plan B.

SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3

(Image credit: OpenFive)

SiFive on Tuesday said that that its OpenFive division has successfully taped out the company’s first system-on-chip (SoC) on TSMC’s N5 process technology. The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs. Meanwhile, elements from this SoC can be licensed and used for other N5 designs without any significant effort.

The SoC contains the SiFive E76 32-bit CPU core(s) for AI, microcontrollers, edge-computing, and other relatively simplistic applications that do not require full precision. It uses OpenFive’s D2D (die-to-die) interface for 2.5D packages as well as OpenFive’s High Bandwidth Memory (HBM3) IP subsystem, which includes a controller and PHY that supports data transfer rates of up to 7.2 Gbps.

The announcement represents a milestone for SiFive and OpenFive, as the SoC is the first RISC-V-based device to be made using a 5nm node. Meanwhile, the announcement also contains two interesting facts. The first one is of course OpenFive’s implementation of an HBM3 solution and its rather bold data transfer rate expectation (2X compared to the fastest HBM2E available today). The second one is OpenFive’s D2D interface for chiplets that uses 16 Gbps NRZ signals with clock forwarding architecture, comprised of 40 IOs per channel, and provides throughput of up to ~1.75Tbps/mm.

(Image credit: OpenFive)

The current design will hardly ever be used ‘as is’, but parties interested in building a high-performance 5nm RISC-V SoC for AI or HPC applications can take it as a the base design and equip it with their own or third-party IP (e.g., custom accelerators, high-performance FP64-capable cores, etc.).

Alternatively, all three key components of the SoC implemented using TSMC’s N5 node — the E76 core, the D2D interface and its physical implementation (which includes built-in PLL, programmable output drivers, and link training state machines), and the HBM3 memory solution (controller, I/O, PHY) — can be licensed separately.

The tape out means that the documentation for the chip has been submitted for manufacturing to TSMC, which essentially means that the SoC has been successfully simulated. The silicon is expected to be obtained in Q2 2021.

RISC-V Raspberry Pi Alternative Edges Closer to Release

(Image credit: CNX-software)

A potential new Raspberry Pi competitor will soon be announced, according to a post on embedded systems blog CNX-Software. Based on the open-source RISC-V instruction set architecture, the Allwinner D1 development board is a credit-card-sized single board computer with a single core XuanTie C906 64-bit RISC-V CPU running at 1GHz along with 1GB of DDR3 RAM.

(Image credit: CNX-software)

The board has a lot in common with the single-board computers we already know and love, though seems to be aimed at the less powerful end of the spectrum. The Raspberry Pi 4 has this board beat for pure computational power. There’s the familiar 40-pin GPIO which we assume is compatible with layout used on the Raspberry Pi but that remains to be seen. Also present on the board is a single full size HDMI 1.4 port, Wi-Fi 4 and Bluetooth, two USB Type-C ports and a single USB 2.0 Type-A, a Micro SD slot, Gigabit Ethernet, a 3.5mm audio jack, plus camera and display connectors which look to be the same format as the CSI and DSI connectors found on the Raspberry Pi. Interestingly, there’s 256MB of onboard flash storage, and a four-pin UART header for debugging.

Allwinner is positioning the board as a ‘multi-media decoding platform’, and CNX’s figures show it’s good for H.265 up to 1080p60 or 4Kp30, and H.264 up to 1080p60 or 4Kp24. The display header can run a touchscreen at up to 1080p60, and the HDMI port hits the 1.4 standard.

The Allwinner D1 Linux RISC-V has the same dimensions as a Raspberry Pi 4 at 3.3 x 2.2 inches (85 x 56 mm) but the overall layout is different enough to prevent Raspberry Pi cases from being used. Beyond its video engine, the Allwinner D1 Linux RISC-V development board doesn’t have much in the way of graphics processing. A quoted Coremark score of 3.8/Mhz doesn’t compare well with the Raspberry Pi 4’s 15.1/MHz, but we’d expect this board to be considerably cheaper, and it could be interesting for use in smart displays or networked cameras. Allwinner has its own Debian-based Linux distribution, Tina OS, though its Github page was last updated in 2017, so we’re hopeful for a newer kernel to go with this new board.

Right now that is all we know, but we are hopeful that this board will introduce the RISC-V platform to more makers and lead to more powerful machines coming in the near future.

Intel hopes to start making chips for car companies within six to nine months

Intel could start producing in-demand semiconductors for car companies within six to nine months, CEO Pat Gelsinger said in an interview with Reuters, commenting that the chipmaking is already being discussed with companies that design chips for cars.

“We’re hoping that some of these things can be alleviated, not requiring a three- or four-year factory build, but maybe six months of new products being certified on some of our existing processes,” Gelsinger told Reuters. “We’ve begun those engagements already with some of the key components suppliers.”

Even if Intel is unable to meet that six to nine month goal, the news highlights the importance that Intel is placing on its new business as a producer of chips for other companies.

Gelsinger unveiled the new business — called Intel Foundry Services — as a “standalone foundry business unit” last month at his “Engineering the Future” announcement, with promises that the company would put its fabs to work producing x86, Arm, and RISC-V core chips for external clients. As part of that announcement, Intel also planned to invest $20 billion into expanding its fabs in Arizona to help it better meet demand from external partners.

The automotive industry has been one of the areas that’s been hit hardest by the ongoing global semiconductor shortage, with car companies like Ford and GM forced to shut down production or make changes to their trucks due to a lack of parts. If Intel is able to start producing automotive chips within the year, it could provide a much-needed new avenue of supply to alleviate those shortages.

The global shortage has reached the point that the Biden administration is looking to intervene: the president has called for a review of the semiconductor supply chain in an executive order and hosted the executives of companies including Intel, Google, Ford, GM, TSMC, and Dell at the White House for today’s “CEO Summit on Semiconductor and Supply Chain Resilience.”

“We’ve been falling behind on research and development and manufacturing, and, to put it bluntly, we have to step up our game,” Biden said at the meeting.

Intel invests $20 billion into new factories, will produce chips for other companies

Intel has a new CEO, Pat Gelsinger, and he’s not wasting any time to make some big changes. At the company’s “Engineering the Future” announcement today, Gelsinger announced plans to outsource more of Intel’s chip production to third-party foundries; a $20 billion investment into two new fabs in Arizona; and a new branch of the company called Intel Foundry Services, which will see Intel’s foundries produce chips for other companies.

The announcements are part of a new “IDM 2.0” strategy for Intel’s design and manufacturing, which is made up of three parts. First, there’s Intel’s in-house manufacturing, which will continue to serve as a key part of Intel’s design and production of chips. Second, there’s an expanded use of external foundries, including TSMC, Samsung, and GlobalFoundries, for production of “products at the core of Intel’s computing offerings” for both consumer and enterprise chips, starting in 2023.

And third, there’s the newly announced Intel Foundry Services, which will see Intel open its gates to handle manufacturing of chips for other commercial customers, led by Randhir Thakur. Intel Foundry Services is a “standalone foundry business unit,” and it will develop x86, Arm, and RISC-V core chips for external clients using Intel’s manufacturing technology. And crucially for government work, Intel’s foundries will be located in the US and Europe, a benefit that competitors like TSMC don’t have. Partners include IBM, Qualcomm, Microsoft, Google, and more.

The expansion of Intel’s manufacturing efforts — which include a $20 billion investment into new fabs in Arizona that will expand Intel’s existing Ocotillo campus — come at a critical time: the ongoing global semiconductor shortage means that demand for chips is at an all-time high. Adding Intel’s foundries (and its new Foundry Services business) could help open up new avenues for companies to source the chips that are essential for everything from new video game consoles to new pickup trucks. Gelsinger also teased that more foundries are in the works, promising additional announcements of expansions in the US, Europe, and elsewhere in the world later this year.

Intel also announced a new R&D collaboration with IBM “focused on creating next–generation logic and packaging technologies.” Details are slim at the moment, however.

Lastly, Intel announced plans to bring back a spiritual successor to its Intel Developer Forum conference with a new Intel Innovation event planned for October in San Francisco this fall as part of a new Intel On series of events.

Intel stands at a critical junction right now: the company faces increased competition from companies like AMD and Apple’s Arm-based M1 series of chips. At the same time, it’s seen major shifts in leadership and delays of generations of its chips, all while being outpaced by competitors like TSMC in terms of production techniques. Today’s announcements represent Gelsinger’s first big moves to try to right the ship.

Chinese Loongson 16-Core MIPS 12nm CPU for 256-Core Servers to Launch Shortly

(Image credit: HKEPC)

Executives of Loongson Technology, a subsidiary of the Chinese Academy of Engineering, said at a recent conference that the next-gen Loongson 5000-series processors were on track to be released this year. The new MIPS64-compatible CPUs are aimed at client PCs as well as multiprocessor servers. Interestingly, the new chips may be the last high-end MIPS64 offerings from the Chinese Academy of Engineering.

The chips in question are the 2.50 GHz quad-core Loongson 3A5000 for client PCs and 16-core Loongon 3C5000 for servers with up to 16 processors. Both chips are set to be made using a 12nm process technology (most likely one of TSMC’s nodes), reports CnTechPost, citing a small conference that was held earlier this year. Both CPUs are said to be based on a new internal architecture that is compatible with the MIPS64 instruction set, feature enlarged caches, and a new memory controller.

Based on some previous reports, the 3A5000 was taped out in April 2020, which is why it is due in the coming months; whereas the 3C5000 was taped out in August, 2020, so it will be released towards the end of 2021 if everything goes as planned.

(Image credit: HKEPC)

One interesting thing about Loongson Technology is that the company is reportedly ‘looking forward to join the open-source instruction consortium.’ The consortium mentioned by Loongson’s executives is almost certainly RISC-V International, which essentially means that going forward, the company will focus on RISC-V.

Loongson has historically developed MIPS-compatible CPU cores, so switching to RISC-V should not be too challenging for the company as the architectures have many similarities. Meanwhile, the adoption of RISC-V means that Loongson’s upcoming processors (or cores) will be supported by a broad ecosystem of software and hardware, something that will inevitably make them more competitive.

Developing new RISC-V-compatible microarchitectures and cores will take several years, so for now, Loongson will have to promote its 3A5000 among PC makers and its 3C5000 among server and HPC customers.

Taiwan Drought Threatens Single Board Computer Production

(Image credit: Shutterstock)

It is true to say that 2020 wasn’t a great year, period. There have been both CPU and GPU shortages in the electronics world, but a recent drought in Taiwan could affect all sectors, including the many single board computers (SBC) such as the Raspberry Pi. TSMC has been asked to reduce its water use by 7%, which should help keep the island’s reserves at sufficient levels until the rainy season ends in May. Could this impact the Raspberry Pi range of boards, including the Pico?

Taiwan Semiconductor Manufacturing Company (TSMC) makes chips for many different customers such as Apple and Intel, so the drought in Taiwan may impact chip production for many different types of consumer electronics. The latest to be affected are the many makers of SBC. In a post on ameriDroid, an unnamed manufacturer states.

“Just wanted to give you a heads up that there are severe component shortages happening globally now; this certainly is affecting all SBC manufacturers such as PINE64, ODROID, and also Raspberry Pi. We are trying to navigate this difficulty and minimize the impact. It looks like this shortage can last a long time, possibly into 2022.” If this turns out to be true, then we could be in for a lean year.

We asked Raspberry Pi creator and Chief Executive of Raspberry Pi Trading, Eben Upton, to comment on this issue. “We’re not expecting any impact from this (or the other factors causing tightness in global supply chains) at present: we’re getting great support from our component vendor partners.”

The impact on some SBC is starting to be felt, and Pine64, makers of cellphones, laptops, and RISC-V powered soldering irons, announced via a tweet that “Due to component shortages, component price-increases & related issues, we will only open orders/pre-orders when production is securely underway. ”

(1/2) [PSA] Re. availability of #PinePhone, #PinebookPro, #PineTab, etc., Due to component shortages, component price-increases & related issues, we will only open orders/pre-orders when production is securely underway. We are more cautious than usual, also for your sake (…) pic.twitter.com/0cJA2dQNpCMarch 11, 2021

Pine64 isn’t the only company to have announced that there could be an impact. In an ODROID forum post, we read that there could be a four to five month delay in chips for the company’s H2+ board. It seems that 2021 could be another year of shortages, but this time on a much larger scale, affecting sectors such as consumer electronics and the automobile industry.

MIPS Starts RISC-V CPU Development

(Image credit: Panasonic)

Wave Computing and its subsidiary MIPS Technologies, the developer of the MIPS processor architecture, recently emerged from Chapter 11 bankruptcy protection, renamed itself to MIPS and changed the business model. As reported by Electronic Engineering Journal the new company will focus on development of RISC-V CPU cores and will abandon further development of its own MIPS architecture.

“Going forward, the restructured business will be known as MIPS, reflecting the company’s strategic focus on the groundbreaking RISC-based processor architectures which were originally developed by MIPS,” a statement by the company reads. “MIPS is developing a new industry-leading standards-based 8th generation architecture, which will be based on the open source RISC-V processor standard.”

MIPS does not get much publicity these days mostly because it is no longer used for game consoles or supercomputers. Yet, the architecture is still among the most popular in the industry. It is widely used for various microcontrollers, consumer electronics SoCs, communication equipment, and a variety of low-power devices. Hundreds of millions of such products are sold every year and for now MIPS cores are good enough for their applications.

It is hard for MIPS to compete against Arm Holdings which has a wider choice of cores and which who’s architecture powers more applications than any other architecture nowadays. It is close to impossible for MIPS to catch up with Arm when it comes to performance and industry support, so the new MIPS decided to change its business model.

Previously MIPS Technologies and later Wave Computing licensed their architecture and cores to processor developers, which made them compete directly against Arm Holdings that has the same business model. Since the MIPS architecture belongs to one company it is solely responsible for the whole ecosystem (which includes hardware and software) and supporting it alone is hard.

From now on, MIPS will develop RISC-V-based architecture and appropriate CPU cores that it will license to others. In general, the licensing nature of MIPS’s business will not change, but since RISC-V is an open standards architecture supported by dozens of companies, MIPS will not have to support the ecosystem alone, which will make its business more sustainable.

MIPS has a lot of expertise in CPU development as well as a broad portfolio of CPU patents and IP. All of these assets will inevitably be used for the upcoming RISC-V-based architecture as well as CPU cores, so it is logical to expect MIPS to be one of the leading RISC-V developers. Whether or not that architecture will be competitive against Arm’s offerings is something that remains to be seen.

Russia’s Elbrus Development: A Homebrew SSD Controller

(Image credit: Kraftway)

Russia’s MCST Elbrus microprocessors made a splash last year, but it takes a lot mot than a microprocessor to develop a completely self-sufficient computing platform. Among other things such nationally-oriented platforms need is a proprietary SSD controller, and apparently server maker Kraftway has developed one and demonstrated it at a conference this week. The chip will enable building encrypted SSDs featuring a proprietary encryption technology.

The Kraftway K1942BK018 is an Arm Cortex-R5-based NVMe 1.2.1-compliant controller with eight NAND channels that supports up to 2TB of flash memory as well as up to 2GB of DDR3 SDRAM cache. The chip features an ONFI 200MHz interface and is compatible with NAND chips produced by Micron and Toshiba and then packaged in Russia by GS Nanotech. The controller connects to the host using a PCIe 2.0 x4 interface and enables building SSDs in an HHHL or U.2 form-factor. The chip is made using TSMC’s 40 nm process technology and comes in a BGA676 package. The developer claims that it consumes from 3.5W to 4W under load.

(Image credit: Kraftway)

The manufacturer claims that the drives powered by the new controller will deliver an up to 828 MB/s read speed as well as an up to 659 MB/s read speed.

(Image credit: Kraftway)

Surprisingly, the Kraftway K1942BK018 supports a rather outdated BCH 96-bit/1K ECC technology, which means that it may not support all modern types of 3D NAND.

(Image credit: Kraftway)

The key feature of the Kraftway K1942BK018 is that it was fully developed in Russia and uses proprietary management algorithms as well as cryptography standards. The primary customers that will use the controller are various government agencies, the ministry of defense, state-controlled companies and other entities interested in maximum security and proprietary algorithms.

Kraftway plans to produce 10,000 SSDs based on its K1942BK018 controller in the coming months in a bid to use them with its PCs aimed at those markets.

Interestingly, but in addition to the Arm Cortex-R5-based K1942BK018 controller there are also two RISC-V-based SSD and USB drive controllers designed in Russia and based on cores developed in Saint Petersburg.

(Image credit: Kraftway)