keyword: TLC

Introduction

In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a “new” banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.

Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.

Last Update (Oct 19th):

• Added AMD Lucienne APU
• Updated AMD Cézanne / Ryzen 5000 APU
• Update AMD Ryzen 5000
• Updated Intel Alder Lake
• Updated Intel Ice Lake Server
• Added Intel Grand Ridge
• Updated Intel Meteor Lake
• Updated Intel Jasper Lake
• Updated AMD Big Navi
• Updated AMD RDNA2
• Updated NVIDIA RTX 3070
• Added NVIDIA RTX 3060 Ti
• Added NVIDIA Ampere Mobile
• Added AMD Radeon RX 6500
• Updated AMD Radeon RX 5300 XT
• Updated Intel Xe Graphics
• Updated AMD CDNA / CDNA2
• Updated Intel 500-Series chipsets
• Updated HBM2E memory
• Added HBMNext memory
• Updated DDR5 memory
• Updated TSMC 5 nanometer, 4 nanometer, 3 nanometer, 2 nanometer
• Removed launched products: Intel Comet Lake KA, Tiger Lake, NVIDIA RTX 3080 / 3090, Ampere, MX450

Processors

AMD Lucienne Zen 2 APUs / Ryzen 5000 [added]

• Release Date: Probably 2021
• Successor to “Renoir”
• Built on Zen 2 CPU cores, but still branded “Ryzen 5000”
• Uses Vega iGPU
• Built on slightly refined 7 nm process, but not N7P or N7+
• Ryzen 3 5300U: 4c/8t, 2.6 GHz base, 3.85 GHz boost, 4 MB L3, 10-25 W TDP, 6 CU @ 1.5 GHz
• Ryzen 5 5500U: 6c/12t, 2.1 GHz base, 4.0 GHz boost, 8 MB L3, 10-25 W TDP, 7 CU @ 1.8 GHz
• Ryzen 7 5700U: 8c/16t, 1.8 GHz base, 4.3 GHz boost, 8 MB L3, 10-25 W TDP, 8 CU @ 1.9 GHz
• Built on TSMC 7 nm process, N7

AMD Cézanne Zen 3 APUs / Ryzen 5000 [updated]

• Release Date: Probably 2021
• Successor to “Renoir”
• Built on Zen 3 CPU cores, paired with Vega iGPU
• Ryzen 3 5400U: 4c/8t, 2.6 GHz base, 4.0 GHz boost, 8 MB L3, 10-25 W TDP, 6 CU @ 1.6 GHz
• Ryzen 5 5600U: 6c/12t, 2.3 GHz base, 4.2 GHz boost, 12 MB L3, 10-25 W TDP, 7 CU @ 1.8 GHz
• Ryzen 7 5800U: 8c/16t, 2.0 GHz base, 4.4 GHz boost, 16 MB L3, 10-25 W TDP, 8 CU @ 2.0 GHz
• Built on slightly refined 7 nm process, but not N7P or N7+
• Similar core counts as predecessors
• 19% IPC uplift on Zen 3 models
• Comes in 15 W and 45 W SKUs
• “Van Gogh” APU is based on Zen 3, too, but uses RDNA2 iGPU, for ultra-low-end

AMD Ryzen 5000 Desktop / Zen 3 [announced]

• Announced: Oct 8, 2020
• Market availability: Nov 5
• Reviews: Nov 5
• Design completed as of Aug 2019
• Codename: Vermeer (CPU)
• CCX removed, so that all cores on the CCD share a single large L3 cache
• Continues to use Socket AM4 for desktop
• Redesigned chiplets with 32+ MB shared L3 on each chiplet, as opposed to 2x 16 MB shared between CCX groups
• Zen 3 processors are compatible with B450, X470, B550 and X570 motherboards (after BIOS flash)
• Ryzen 5 5600X: 6c/12t, 3.7 GHz base, 4.6 GHz boost, 65 W TDP, 32 MB cache, $299
• Ryzen 7 5800X: 8c/16t, 3.8 GHz base, 4.7 GHz boost, 105 W TDP, 32 MB cache, $449
• Ryzen 7 5900X: 12c/24t, 3.7 GHz base, 4.8 GHz boost, 105 W TDP, 64 MB cache, $549
• Ryzen 9 5950X: 16c/32t, 3.4 GHz base, 4.9 GHz boost, 105 W TDP, 64 MB cache, $799
• Ryzen 5 5600: Launches 2021 at $220
• Far Cry 6 game bundle included (in select markets)
• PCIe Gen 4
• Up to 19% IPC improvement
• 24% better energy efficiency, 2.8x efficiency vs. Core i9-10900K
• Up to 50% faster floating point
• New CPU core

AMD Zen 3 [announced]

• Release date: 2021 (Server / Threadripper)
• Design completed as of Aug 2019
• Codename: Vermeer (CPU), Dali (APU w/ IGP), Milan (Server), Grey Hawk (Embedded), Genesis Peak (Threadripper)
• Zen 3 refresh, possibly based on improved tech called “Warhol”
• CCX removed, so that all cores on the CCD share a single large L3 cache
• Redesigned chiplets with 32+ MB shared L3 on each chiplet, as opposed to 2x 16 MB shared between CCX groups
• Server platform codename “Genesis SP3”
• Up to 64-cores (128-threads) across eight 8-core chiplets
• 120 – 225 W TDP
• Clock frequencies: up to 3.8 GHz base, up to 4.9 GHz boost
• 64-core EPYC Milan clocked at 3.0 GHz
• PCIe Gen 4
• 8-channel DDR4 memory
• New process tech: 7 nm Plus (probably not 7 nm+ EUV)
• 20% increase in transistor density, 10% lower power consumption
• Up to 15% IPC improvement + more from higher clock frequencies
• Up to 50% faster floating point
• Possibly support for AVX-512
• New CPU core

AMD Zen 4

• Release Date: 2021
• “In Design” as of Nov 2018
• “On Track” for 2021 launch as of Dec 9, 2019
• 5 nm TSMC process
• DDR5 memory support
• Improves IPC
• Server platform codenamed “Genoa”
• PCI-Express Gen 5
• More cores per chiplet
• Uses 3rd generation Infinity Fabric, which adds cache-coherent unified memory
• Uses Socket SP5 for EPYC, new mainstream socket expected (AMD Socket AM5)

AMD Zen 5

• Release Date: 2022
• 5 nm or 3 nm TSMC process
• DDR5 memory support
• PCI-Express Gen 5
• Desktop codename: “Raphael”
• APU codename: “Rembrandt”
• Uses Socket SP5 for server, desktop uses Socket AM5

Intel Ice Lake Server [updated]

• Release date: late 2020, re-confirmed as of Q2 2020
• Ice Lake mobile was launched in late 2019
• Ice Lake desktop was scrapped because it wasn’t competitive with Comet Lake
• Xeon codename “Whitley”
• Uses new 4189-pin LGA socket
• 8-channel DDR4 interface
• 10 nanometer DUV (deep-ultraviolet) process
• Brand-new CPU core design codenamed “Sunny Cove”
• PCI-Express Gen 4.0
• “GenuineIntel Family 6 Model 106 Stepping 4” processor: 24c/48t, 2.2 GHz base, 2.9 GHz boost, L1D 48 KB, L1I 32 KB, L2 1.25 MB, L3 36 MB
• “GenuineIntel Family 6 Model 106 Stepping 5” processor: 28c/56t, 1.5 GHz base, 3.5 GHz boost, L1D 48 KB, L1I 32 KB, L2 1.25 MB, L3 42 MB
• 2x 28c CPU Geekbench SP = 3424, MP = 38079, EPYC 7742: SP = 4398, MP = 35492
• Adds AVX512 instructions (so far available only on HEDT platform, since Skylake-X). New instructions: AVX512F, AVX512CD, AVX512DQ, AVX512BW, and AVX512VL. New commands: AVX512_IFMA and AVX512_VBMI
• 20-30% broadening of various number crunching resources, wider execution window, more AGUs
• 18% IPC gains vs Cascade Lake
• SHA-NI and Vector-AES instruction sets, up to 75% higher encryption performance vs. “Skylake”
• Supports unganged memory mode
• Integrated GPU based on new Gen11 architecture, up to 1 TFLOP/s ALU compute performance
• Integrated GPU supports DisplayPort 1.4a and DSC for 5K and 8K monitor support
• Gen11 also features tile-based rendering, one of NVIDIA’s secret-sauce features
• Integrated GPU supports VESA adaptive V-sync, all AMD FreeSync-capable monitors should work with this
• Ice Lake introduces Intel TME (Total Memory Encryption), also Intel Platform Firmware Resilience (Intel PFR)

Intel Core i9-10990XE

• Release Date: unknown, originally early 2020, seems cancelled now
• 22-cores + HyperThreading
• Uses Cascade Lake-X architecture
• LGA2066 Socket
• 1 MB L2 cache per core, 30.25 MB shared L3 cache
• 4 GHz base, up to 5 GHz boost
• Roughly matches Threadripper 3960X in Cinebench
  
  

Intel Rocket Lake [updated]

• Release Date: Q1 2021
• Succeeds “Comet Lake”
• Variants: Rocket Lake-“S” (mainstream desktop), -“H” (mainstream notebook), -“U” (ultrabook), and -“Y” (low power portable)
• 14 nanometer production process
• Seems to be limited to eight cores (2 less than 10-core Comet Lake)
• Some indication of mixed HyperThreading configurations, for example 8-core, 12-thread
• Uses “Cypress Cove” core, which seems to be a backport of “Willow Cove” to 14 nm process
• Up to 10% IPC improvement over Skylake
• No FIVR, uses SVID VRM architecture
• 125 W maximum TDP
• Compatible with 400-series chipsets
• Possible they release 500-series chipsets with added features
• Socket LGA1200 (just like Comet Lake)
• Supports PCI-Express 4.0
• 20 PCIe lanes
• Intel Xe integrated graphics, based on Gen 12 with HDMI 2.0b and DisplayPort 1.4a
• Xe EU count only 32, Tiger Lake will have 96
• 2.5 Gb/s Ethernet, Thunderbolt 4, USB 3.2 20G
• iGPU with up to 32 EUs
• Memory support: DDR4-2933
• 32 KB L1I cache, 48 KB L1D cache, 512 KB per core L2 cache, and 16 MB shared L3 cache (8-core chip)
• Engineering Sample: Family 6, Model 167, Stepping 0, 8c/16t, 3.4 GHz base, 5.0 GHz boost
• Engineering Sample: Family 6, Model 167, Stepping 0, 8c/16t, 3.2 GHz base, 4.3 GHz boost

Intel Willow Cove and Golden Cove Cores

• Release Date: 2021
• Succeeds “Sunny Cove”
• Willow Cove improves on-die caches, adds more security features, and takes advantage of 10 nm+ process improvements to increase clock speeds versus Sunny Cove
• Golden Cove will add significant single-thread (IPC) increases over Sunny Cove, add on-die matrix multiplication hardware, improved 5G network-stack HSP performance, and more security features than Willow Cove

Intel Alder Lake [updated]

• Release Date: H2 2021
• Mixes CPU cores of various processing power (and energy consumption), similar to the Big.Little-like designs for mobile devices
• Combines up to eight Golden Cove with up to eight Gracemont (Atom) cores
• These cores have two different instruction sets, for example Golden Cove has AVX-512, TSX-NI and FP16, which Gracemont lacks
• 10 nm process
• Uses Socket LGA1700
• Alder Lake for desktop: 37.5 mm x 45 mm package
• Desktop CPUs come in 125 W and 80 W
• Could use Foveros 3D Stacking technology
• Possible CPU configurations 8+8+1 (8 big cores, 8 small cores, GT1 integrated), and 6+0+1 (6 big cores, no small cores and GT1 integrated)
• Includes Gen12 Xe iGPU
• DDR5 memory support
• PCI-Express 5.0 support
• Includes CLDEMOTE instruction, to invalidate cache lines

Intel Sapphire Rapids

• Release Date: H2 2021
• Successor to Cooper Lake
• 8-channel DDR5
• Uses Socket LGA4677
• For enterprise / data center
• 10 nm+ production process
• Willow Cove CPU cores
• PCIe 5.0
• Probably 7 nm process
• Platform name: Eagle Stream
• Includes CLDEMOTE instruction, to invalidate cache lines

Intel Grand Ridge [added]

• Release Date: 2022 or later
• Produced on 7 nm HLL+ process
• Successor to Atom “Snow Ridge”
• 24 cores across 6 clusters with 4 cours each
• 4 MB L2 per cluster, plus L3 cache
• Uses Gracemont CPU core
• Dual-channel DDR5
• PCI-Expres Gen 4 with 16 lanes

Intel Elkhart Lake

• Release Date: Unknown
• Produced on 10 nm process
• Designed for next-gen Pentium Silver and Celeron processors
• CPU cores use Tremont architecture
• GPU uses Gen 11
• Dual-core and Quad-core configurations
• Single-channel memory controller with DDR4 and LPDDR4/x support
• Engineering sample: 1.9 GHz, 5/9/12 W TDP

Intel Meteor Lake [updated]

• Release Date: 2022 or 2023
• Succeeds “Alder Lake”
• New microarchitecture, more advanced than “Willow Cove”, possibly “Golden Cove”
• As of late 2020 Intel is adding support for Meteor Lake to the Linux Kernel
• Produced on 7 nm EUV Intel process

Intel Jasper Lake [updated]

• Release Date: Unknown
• Uses Tremont architecture
• 10 nm production process
• Successor to Gemini Lake
• ES: 4c/4t, 1.1 GHz Base, 1.12 GHz Boost
• DDR4 memory support
• Pentium Silver J6005: 4c/4t, 2 GHz base, 3 GHz boost, 4 MB L2
• Celeron J5105: 2 Ghz vase, 2.8 GHz boost, 4 MB L2
• Celeron J4505: 2c/2t, 2 GHz base, 2.9 GHz boost 4 MB L2
• Pentium Silver N6000 Mobile: 4c/4t, 1.1 GHz base, 3.1 GHz boost, 4 MB L2
• Celeron N5100 Mobile: 1.1 GHz base, 2.8 GHz boost
• Celeron N4500 Mobile: 2c/2t, 1.1 GHz base, 2.8 GHz boost

Intel Granite Rapids

• Release Date: 2022
• Successor to Sapphire Rapids
• 8-channel DDR5
• For enterprise / data center
• PCIe 5.0
• Probably 7 nm+ process
• Platform name: Eagle Stream

VIA CenTaur / Zhaoxin KaiXian

• Release Date: H2 2020
• Eight-core 64-bit CPU, 2.5 GHz
• AVX-512 supported
• 16 nm FinFET TSMC
• 195 mm² die size
• Use LGA socket
• Codename: “CHA”, pronounced “C-H-A”
• Separate AI co-processor “NCORE”
• All cores + NCORE connected using a ring bus
• Integrated VIA S3 graphics with DirectX 11.1
• 16 MB shared L3 cache
• Four-channel DDR4-3200 memory support
• 44 PCI-Express 3.0 lanes
• Sold as Zhaoxin KaiXian KX-6780A in China (end of Jan 2020): 8 core, 8 threads, 2.7 GHz, 8 MB cache, dual-channel DDR4-3200
• Southbridge integrated
• Multi-socket capable

Graphics / GPUs

NVIDIA RTX 3070 [updated]

• Release Date: Oct 29 2020
• Based on GA104 GPU
• GA104-400 for RTX 3070, 5888 CUDA cores, 1.5 GHz base, 1.73 GHz boost, 256-bit GDDR6 memory, $499
• RTX 3070 Ti rumored with 16 GB, GDDR6X, GA104-300

NVIDIA RTX 3060 [added]

• Release Date: 2020 or 2021
• 8 GB GDDR6
• Matches RTX 2080 performance

NVIDIA RTX 3060 Ti [added]

• Release Date: 2020 or 2021
• GA104 GPU, same as RTX 3070
• 4864 shaders, 38 RT cores, 152 tensor cores, 152 TMUs
• 8 GB GDDR6, 256-bit
• 180 – 200 W TDP, 1x 8-pin power
• Gigabyte GeForce RTX 3060 Ti Aorus Master 8G (GV-N306TAORUS M-8GD), Gigabyte GeForce RTX 3060 Ti Gaming OC 8G (GV-N306TGAMING OC-8GD), Gigabyte GeForce RTX 3060 Ti Eagle OC 8G (GV-N306TEAGLE OC-8GD), and the Gigabyte GeForce RTX 3060 Ti Eagle 8G (GV-N306TEAGLE-8GD)

NVIDIA Ampere with more VRAM

• Release Date: December 2020
• RTX 3080 with 20 GB memory (instead of 10 GB)
• RTX 3070 with 16 GB memory (instead of 8 GB)

NVIDIA RTX 3000 Mobile Ampere [added]

• Release Date: 2021
• RTX 3070 Mobile (Max Q), H56C8H24AIR GDDR6 memory

NVIDIA Ampere Refresh

• Release Date: unknown
• NVIDIA is moving their existing designs from Samsung 8 nm to TSMC 7 nm

NVIDIA Hopper

• Release Date: unknown
• Successor to “Ampere” architecture
• MCM (multi-chip module) GPU packages
• Seems to be for workstation/compute only

AMD Radeon RX 5300 XT [updated]

• Release date: unknown
• Non-XT version has launched on Aug 31, 2020 (1408 cores, 3 GB GDDR6, 96-bit, 1448 MHz game clock, 1645 MHz boost, 100 W TDP)
• 24 Compute Units / 1536 Stream Processors
• 3 GB GDDR6 memory, 96-bit
• 7 nanometer production process
• Probably based on Navi 14 GPU

AMD Radeon RX 5600M and RX 5700M

• Release date: unknown
• Based on Navi 10 silicon
• 7 nanometer production process
• RX 5700M: 2304 shaders, 144 TMUs, 64 ROPS, 8 GB GDDR6 memory, 256-bit, 1620-1720 MHz
• RX 5600M: 2304 shaders, 144 TMUs, 64 ROPS, 6 GB GDDR6 memory, 192-bit, 1190-1265 MHz

Big Navi / Navi 20 / Navi 21 / Radeon RX 6000 Series [updated]

• Release Date: Late 2020
• Announcement: October 28
• Uses RDNA2 graphics architecture
• 7 nanometer, possibly 7 nm+ EUV
• Codename could be “Sienna Cichlid”
• Goes up against NVIDIA high-end Ampere
• Radeon RX 6000 Series: Radeon RX 6900, RX 6900 XT, RX 6900 XTX
• Navi 21: 2x Navi 10, 80 CU, 5120 Stream Processors, 16 GB GDDR6, 255 W TGP, 2.4 GHz Game Clock, 536 mm² die size, dual 8-pin power inputs, 2x DP, 1x HDMI, 1x USB-C
• 4K performance slightly below RTX 3080, Borderlands 3: 61 FPS, COD MW: 88 FPS, Gears 5: 73 FPS
• Aims to provide playable 4K framerates
• Features “Infinity Cache”
• Lisa Su in a CES 2020 interview said “we will have a high-end Navi […] it is important”
• AMD CFO: “Big Navi” will be a halo product and not merely a lofty performance increase over the RX 5700 XT to make AMD competitive against GeForce “Ampere.”
• Adds support for DirectX 12 Ultimate: variable-rate shading and hardware-accelerated ray-tracing (DXR version 1.1)

AMD RDNA 2 [updated]

• Announcement: October 28
• Lisa Su: “we will have our new next-generation RDNA architecture that will be part our 2020 lineup”
• TSMC, 7 nm Plus (probably not 7 nm+ EUV)
• Up to 18% higher transistor density
• Higher clock speeds than RDNA
• 50% better performance per Watt than RDNA, twice the efficiency as GCN
• Adds variable rate shading
• Adds support for BFloat16
• Adds AV1 video decode hardware acceleration
• Adds hardware raytracing acceleration (DXR version 1.1)
• Supports Microsoft DirectX 12 Ultimate API /DXR, VRS, Mesh Shaders & Sampler Feedback)
• Same GPU architecture powers PlayStation 5 & Xbox Series X

AMD Radeon RX 6500 [added]

• Release date: unknown
• 40 Compute Units / 2560 Stream Processors
• 192-bit GDDR6 memory
• 7 nanometer production process
• RDNA2 architecture
• Codename “Navy Flounder”
• Below $250

AMD RDNA 3

• Release Date: Late 2021 or 2022
• “Advanced Node”, probably TSMC 6 nm or 5 nm

AMD CDNA and CDNA2 [updated]

• Release Date: 2020 for CDNA and 2021-2022 for CDNA2
• New architecture that focuses on compute for “Radeon Instinct”
• TSMC 7 nm or 7 nm+
• 128 Compute Units = 8192 shaders
• Arcturus engineering sample has 120 CUs (7680 shaders), 878 MHz for the core clock, 750 MHz SoC clock, and 1200 MHz memory clock
• Compute only—Rasterization, display controllers and media encoding hardware removed
• Product name: Radeon Instinct MI100, 120 CU / 7680 cores, 32 TFLOP FP32
• 1000 MHz memory clock: 1 TB/s memory bandwidth
• GPU clock up to 1334 MHz
• 200 W TDP
• CDNA seems to be very similar to Vega
• Add Tensor cores like on NVIDIA
• Uses 32 GB HBM2 or HBM2E memory from Hynix and Samsung
• Infinity Fabric link to pool multiple GPUs
• CDNA2 implements Infinity Fabric gen 3.0 to support vast memory pools and cache-coherent unified memory access
• Adds support for BFloat16

Intel Xe Discrete Graphics [updated]

• Release Date: 2021 for discrete GPU
• Intel has scheduled a presentation event for August 13th, also Hot Chips Conference presentation on August 17th
• Announcement: Xe DG1-SDV (Software Development Vehicle) announced at CES 2020 (Jan 9th 2020)
• First Intel Discrete GPU since ill-fated Larrabee
• New architecture built from the ground up, and not an upscale of Gen 11
• Developer kit shipping as of Q4 2019, called “Discrete Graphics DG1 External FRD1 Accessory Kit (Alpha) Developer Kit”
• Intel DG2: 8 GB GDDR6, Tiger Lake-H CPU, 256-bit memory bus, 512 EU
• SDV OpenCL performance in Geekbench: 55373 points, with 3.53 Gpixels/s in “Sorbel,” 1.30 Gpixels/sec in Histogram Equalization, 16 GFLOPs in SFFT, 1.62 GPixels/s in Gaussian Blur, 4.51 Msubwindows/s in Face Detection, 2.88 Gpixels/s in RAW, 327.4 Mpixels/s in DoF, and 13656 FPS in Particle Physics. Roughly matches 11 CU Vega Picasso IGP
• SDV is 15.2 cm long, 96 Execution Units, PCI-Express x16, slot only power (so 75 W), 3x DisplayPort, 1x HDMI, high noise levels
• Up to 2x performance uplift for Intel Xe integrated graphics over previous Gen 11
• Using a multi-chip design approach, with Foveros, Intel Xe scales up to 512 EUs with 500 W
• 512 EU model is datacenter only, 300 W 256 EU model for enthusiast markets
• Targeted at 1080p gameplay, CES demonstration showed working gameplay on Destiny 2
• Could be produced at Samsung to leverage their 10 nm tech, while Intel ramps up its own
• Future Xe GPUs could be built on TSMC 6 nm and 3 nm nodes
• Raytracing hardware acceleration support will definitely be included on the data-center GPUs (and probably on the consumer models, too)
• Double-digit TFLOP/s scaling all the way up to 0.1+ PFLOP/s
• Will be used in upcoming Cray Aurora Supercomputer for Argonne National Laboratory in 2021
• Targeting a wide segment of markets, including consumer (client-segment) graphics, enthusiast-segment, and data-center compute
• Uses new graphics control panel that’s being introduced during 2019

Intel Discrete GPU / Arctic Sound

• Release Date: 2020
• Intel will hold a world tour in 2019, to build enthusiasm for the new architecture
• Advanced management for power and clocks
• Test chip: 8×8 mm² die area, 1.54B transistors, 14 nm, 50-400 MHz clock, EUs at 2x clock if needed
• Raja Koduri who left AMD in late 2017 is somehow involved
• Confirmed to support VESA Adaptive Sync

Intel Ponte Vecchio

• Release Date: 2021 or 2022
• Discrete GPU
• Produced on 7 nanometer production process
• Probably not 7 nanometer Intel but 7 nm TSMC or even 6 nm TSMC
• Multiple GPU dies will be combined into a single accelerator
• Architected “for HPC modeling and simulation workloads and AI training”
• Workloads can be processed by GPU and CPU at the same time, using Intel oneAPI
• Foveros packaging technology
• Xe link to combine multiple GPUs (CXL interconnect)

Intel Jupiter Sound

• Release Date: 2022
• Discrete GPU
• Produced on 10 nanometer production process
• Successor to Arctic Sound

Zhaoxin Discrete GPU

• Release Date: Unknown
• Discrete GPU
• Produced on 28 nanometer production process
• 70 Watt TDP
• Based on VIA S3 graphics IP

Chipsets

Intel 500 Series Chipsets [updated]

• Release Date: 2021, possibly March
• For Rocket Lake processors
• Models: Z590 (overclockers), H570 (premium desktop), B560 (midrange desktop), H510 (entry-level desktop), Q570 (commercial desktop), W580 (workstation)
• Socket LGA1200
• PCI-Express 4.0
• 2.5 Gb/s Ethernet, Thunderbolt 4, USB 3.2 20G

AMD 600-Series Chipsets

• Release Date: September 2020, at the same time as Zen 3.
• Highly likely these were scrapped when AMD decided to enable compatibility with 400 and 500 series chipsets
• Socket AM4
• Supporting Zen 3 Ryzen 4000 processors
• Support for older CPUs very likely, probably at least Ryzen 3000
• PCI-Express 4.0

Memory

DDR5 System Memory [updated]

• Release Date: Late 2020, probably 2021
• JEDEC standard finalized as of Jul 15th 2020
• Demo’d in May 2018 by Micron: DDR5-4400
• Samsung 16 Gb DDR5 DRAM developed since February 2018
• Samsung has completed functional testing and validation of a LPDDR5 prototype: 10 nm class, 8 Gbit, final clocks: DDR5-5500 and DDR5-6400
• Samsung has started 16 Gb LPDDR5 mass production in Aug 2020
• SK Hynix 4800 – 5600 Mbps, 1.1 V
• SK Hynix also has 16 Gb DDR5-5200 samples ready, 1.1 V, mass production expected 2020
• April 2020: Hynix has 8.4 Gbps DDR5, minimum density per die is 8 Gbit, maximum is 64 Gbit
• ECC is now supported by all dies (no longer specific to server memory modules)
• SK Hynix demonstrated DDR5 RDIMM modules at CES 2020: 4800 MHz, 64 GB
• Micron is shipping LPDDR5 for use in Xiaomi phones (Feb 2 2020). 5.5 Gbps and 6.4 Gbps
• Samsung has begun production for LPDDR5 for mobile devices (Feb 25 2020). 16 GB, 5.5 Gbps
• 4800 – 6400 Mbps
• Expected to be produced using 7 nm technologies
• 32 banks, 8 bank groups
• 64-bit link at 1.1 V
• Burst length doubled to BL16
• Bank count increased from 16 to 32
• Fine grain refresh feature
• Improved power efficiency enabled by Vdd going from 1.2 V to 1.1 V as compared to DDR4
• On-die ECC
• Voltage regulators on the DIMM modules
• AMD DDR5 memory support by 2021/2022, with Zen 4

HBM2E Graphics Memory [updated]

• Release Date: 2020
• Offers 3.2 Gbps per pin (33% faster than HBM2)
• Rambus offers a 4.0 Gbps memory interface controller
• Samsung Flashbolt: 16 Gb per die, 8-layers stacked, 16 GB per chip with 410 GB/s bandwidth
• Hynix: 460 GB/s, 3.6 Gbps, eight 16 Gb chips are stacked for a single 16 GB chip
• Hynix: mass production has started as of July 2020

HBM3 Graphics Memory

• Release Date: Not before 2019
• Double the memory bandwidth per stack (4000 Gbps expected)
• Expected to be produced using 7 nm technologies

HBMNext Memory [added]

• Release Date: Late 2022 or 2023
• JEDEC work in progress
• Micron involved

GDDR6X Graphics Memory

• Release Date: 2020
• Will first be used on new GeForce RTX 3000 / Ampere Series

Silicon Fabrication Tech

TSMC 7 nanometer+

• Release Date: Q4 2019
• TSMC N7+ is successor to original 7 nm node
• Uses EUV (Extreme Ultra Violet)
• 15-20% more density and improved power consumption over N7

TSMC 6 nanometer

• Release Date: Unknown
• Backwards compatible with 7 nm process—no new design tools needed
• Uses EUV (Extreme Ultra Violet), up to four EUV layers
• 18% higher logic density than N7

TSMC 5 nanometer [updated]

• Release Date: March 2020 to tape-out customer designs
• Risk production as of Q2 2019
• High volume production: Q2 2020
• Uses TSMC’s second implementation of EUV (Extreme Ultra Violet)
• Up to 1.8x the density of 7 nm
• Up to 14 layers
• +15% higher clocks
• 30% better bower than N7
• Intel might be a customer of this node
• N5P “Plus” node: improvement to N5 while staying on 5 nm, 84-87% increase in transistor densities over N7

TSMC 5 nanometer+

• Release Date: 2021
• High-volume production in Q4 2020
• Uses EUV (Extreme Ultra Violet)

TSMC 4 nanometer [updated]

• Mass production: 2023
• Codename “N4”
• Uses EUV lithography

TSMC 3 nanometer [updated]

• April 2020: On-Track
• Risk production: 2021
• Volume production: H1 2022
• FinFET technology
• Uses TSMC’s third implementation of EUV (Extreme Ultra Violet)
• 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed, compared to N5.
• 55,000 water per month at the start, 100,000 by 2023

TSMC 2 nanometer [updated]

• No details known other than “TSMC has started development”
• June 2020: TSMC is accelerating R&D
• Sep 2020: Fab construction has begun
• Will use Gate-All-Around (GAA) technology

Samsung 6 nanometer

• Release Date: Unknown
• First product taped out as of Q2 2019
• Uses EUV (Extreme Ultra Violet)
• Special variant for customers

Samsung 5 nanometer

• Release Date: 2020
• Ready for customer sample production as of Q2 2019
• Mass production in Q2 2020
• Yields are challenging as of Q2 2020
• Uses EUV (Extreme Ultra Violet)
• Up to 25% the density of 7 nm
• 20% lower power consumption
• 10% higher performance

Samsung 3 nanometer

• Release Date: 2022
• 50% less power while delivering 30% more performance
• 45% less silicon space taken per transistor (vs 7 nm)

Intel 7 nanometer

• Release Date: 2022 or 2023
• Succeeded by 7 nm+ node in 2022, and 7 nm++ in 2023
• Uses EUV (Extreme Ultra Violet)
• 4x reduction in design rules
• Planned to be used on multiple products: CPU, GPU, AI, FPGA, 5G networking

Other

Hynix 4D NAND

• Release Date: H1 2019
• Developed by SK Hynix
• Sampling in Q4 2018
• Products demonstrated at CES 2020: Platinum P31 M.2 NVMe and Gold P31—PCIe 3.0 x4, using flash, DRAM and controller made by Hynix, over 3 GB/s read/write.
• Reduces chip physical size, while increasing capacity at the same time
• Supports TLC and QLC
• 30% higher write and 25% higher read performance
• 1.2 V
• 1st generation: 96 stacks, 1.2 Gbps per pin, 512 Gbit TLC
• 128 stacks in development, scales up to 512 stacks

Toshiba 5-Bit-per-Cell NAND Flash (PLC)

• Release Date: Unknown
• Stores an additional bit of information per cell (compared to QLC)
• 32 states per cell
• Will enable even cheaper SSDs, probably with a performance cost

Toshiba XL-Flash

• Developed by Toshiba
• Uses existing SLC flash technology to improve latencies
• 1/10th the read latency of TLC
• Good for random IOPS and better QoS at shallow queue depth
• Can combine SLC and TLC/QLC for tiered, cost-optimized storage
• Intel Optane memory competitor
• 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
• 4 KB page size for more efficient operating system reads and writes
• 16-plane architecture for more efficient parallelism
• Fast page read and program times

Micron 128-layer 3D NAND Flash

• Release Date: 2020, taped out as of Q4 2019
• CMOS-under-array design, but with Replacement Gate (RG) Technology instead of Floating Gate
• Only for few applications, more focused on next-generation RG tech, which brings down cost, too

Toshiba 128-layer 3D NAND Flash

• Release Date: 2020 or 2021
• Developed by Toshiba and partner Western Digital
• Called BiCS 5
• According to a press release in Feb 2020, this is actually a 112 layer stacking process
• Cells are TLC (not QLC)
• Chip density: 512 Gb
• Write performance per channel doubled to 133 MB/s

Intel 144-layer 3D NAND Flash

• Release Date: 2020
• Supports QLC, but can be configured to work as TLC or SLC
• SSD codename “Keystone Harbor”
• PLC (5-bit per cell) technology development is underway
• Optane product codename “Alder Stream”, PCIe Gen4

SK Hynix 128-layer 3D NAND Flash

• Mass Production: July 2020
• Up to 1 Tb TLC flash per chip
• Data rate up to 1400 Mbps at 1.2 V
• Products will be 2 TB client SSD with in-house controller and 16 TB / 32 TB NVMe datacenter SSDs.

Samsung 160-layer 3D NAND Flash

• Release Date: End of 2020
• 7th generation V-NAND

Intel CXL Interconnect

• New interconnect for high-bandwidth devices like GPUs
• Targeted at enterprise and servers
• Competitor to NVLink, Infinity Fabric and PCI-Express
• Uses PCIe physical layer
• Link layer designed for low latency
• 32 Gbps per lane, per direction (Like PCIe Gen 5.0)

PCI-Express 5.0

• Specification released end of May 2019
• Products not expected before 2020
• 32 GT/s bandwidth per lane, per direction (4x the bandwidth of PCIe 3.0)
• 128/130 bit encoding (= 1.5% overhead)
• Implements electrical changes to improve signal integrity and mechanical performance of connectors
• Physical connector